Forum Discussion
Altera_Forum
Honored Contributor
17 years agoTo get more clock detail, modify your report_timing to "-detail full_path". This breaks out your clock into more line items. It's way too much informaiton when your clocks are right, but is very useful when identifying the clock paths and their delay sub-components. Also, a common misunderstanding is to think set_max_delay is a requirement on the delay between registers. In reality it just overrides your setup requirement(which is your clock period within a domain). This way it still takes into account clock skews, which is good.