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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timequest and clock network delays

I'm somewhat new to timequest and timing closure on FPGAs, and I'm finding some things with the use of timequest to be ... strange, in my opinion. This is somewhat related to http://alteraforum.com/f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It seems that 2.9ns set_max_delay is actually causing this (found where is was being set). And I found where the destination clock delay is reported (data required path section).

I think I answered all my questions.