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SrLam9's avatar
SrLam9
Icon for New Contributor rankNew Contributor
7 years ago

TimeQuest Analyzer. False unconstrained clock?

Hi, In the timing analysis of my design, I have one unconstrained clock: csr_control_data_reg[0] which is the control register for the serial flash controller II IP core. The CSR is connected to the...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi SrLam9,

Upon checking, csr_control_data_reg [0] in Serial Flash Controller II Intel FPGA IP is not a clock. It can be safely ignored.

Thanks.