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SrLam9's avatar
SrLam9
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8 years ago

TimeQuest Analyzer. False unconstrained clock?

Hi, In the timing analysis of my design, I have one unconstrained clock: csr_control_data_reg[0] which is the control register for the serial flash controller II IP core. The CSR is connected to the...
SrLam9's avatar
SrLam9
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8 years ago

Hi,

Serial Flash Controller II Intel FPGA IP.

I have it named epcq_controller2_0 in my platform designer project.

Thank you