Forum Discussion
SrLam9
New Contributor
8 years agoTimeQuest Analyzer. False unconstrained clock?
Hi, In the timing analysis of my design, I have one unconstrained clock: csr_control_data_reg[0] which is the control register for the serial flash controller II IP core. The CSR is connected to the...
sstrell
Super Contributor
8 years agoYou can't false path something the tool considers a clock path. False path only prevents data path analysis on the path, not clock path analysis. If this path is indeed going to the clock input of the IP, you need a create_clock (or more likely create_generated_clock) constraint.
What I don't understand is why a CSR path is being considered a clock path in your design. I haven't used that IP, so maybe you need to check the IP's user guide to figure out what's going on here.