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SrLam9's avatar
SrLam9
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8 years ago

TimeQuest Analyzer. False unconstrained clock?

Hi, In the timing analysis of my design, I have one unconstrained clock: csr_control_data_reg[0] which is the control register for the serial flash controller II IP core. The CSR is connected to the...
SrLam9's avatar
SrLam9
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8 years ago

Hi KYeoh,

The full path is :

hps:u0|hps_altera_epcq_controller2_180_y5ic34y:epcq_controller2_0|hps_altera_asmi_parallel2_180_2o4p2ly:asmi2_inst_epcq_ctrl|hps_altera_asmi2_csr_controller_180_rio6xka:csr_controller|csr_control_data_reg[0]

that is the path/signal it shows me in the TimeQuest Clock Status Summary window.

Hi a_x_h_75,

I definitely need to familiarize myself more with TimeQuest.

Thank you