Honored Contributor
Honored ContributorI'm not an expert, too, so please don't take this as the Bible.
Anyway I think the problem is due to the fact that virtual clock has a 30ns setup relationship with internal clock, since TQ assumes it is generated outside fpga, synchrounously to internal clock. So the virtual clock has no delay at all when latching/launching I/O data, while I/O data itself has the delay. On the other hand, the internal clock accounts for the delay required to reach the I/O, which makes no sense for data clocked externally. Infact, TQ guide recommends not using an internal clock with set_input/output_delay, unless you use a generated clock which actually feeds an output pin. PS: you should see what I explained above if you analyze the full path with TQ in both cases. Regards
