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Altera_Forum
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13 years ago

TimeQuest & source-synchronous center-aligned input

Hi, I need to constrain a source-synchronous center-aligned input and I've been reading some Altera documentation, as well as Rysc's guide. However I am still not sure if I am doing the right t...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

So these constraints should be now correct, right?

create_clock -name rxclk1 -period 40 [get_ports {rx_clk_1}]# clock pin

create_generated_clock -name virtual_rxclk1 -source [get_ports {rx_clk_1}] -divide_by 1 -multiply_by 1 -phase 180

set_input_delay -clock { virtual_rxclk1 } -max 10 [get_ports {rx_data_1[*] rx_dv_1}]

set_input_delay -clock { virtual_rxclk1 } -min -10 [get_ports {rx_data_1[*] rx_dv_1}]

Thanks again for the help!