Honored Contributor
Honored ContributorThese are confusing, so please verify that I'm reading it right. I assume the screenshot is of the transmitter, and it's Tsu and Th is saying what spec it can provide to the receiver. Is this SDR(single data rate or DDR)? I'm assuming SDR from the set_input_delay constraints(you only have 2, where DDR would have 4 assignments, basically two more with -add_delay -clock_fall). But if it's SDR, I don't know why it's only doing a 90 degree phase-shift. It's generally either 0 degrees(meaning it can't phase-shift) or 180 degrees.
Being center-aligned, I would say the virtual clock is phase-shifted 180 degrees. That will give you a setup relationship of 20ns and hold relationship of 20ns. Your external delays of +/-10ns cut into that, leaving 10ns for the FPGA's setup analysis(i.e. a 10ns Tsu) and -10ns for hold timing(i.e. a 10ns Th). And looking at it more, it can't be DDR since that would be a 20ns data rate, and if 10ns Tsu and 10ns Th would use the entire data period. Let me know if that doesn't make sense.
