Honored Contributor
Honored ContributorI'm not really worried about the delay in the division operation since I have 2us in the worst case to get the result. I basically then average these values over a period, i.e. slow operation. I just want to make sure Quartus knows what I'm doing so it well tell me I'm meeting timing requirements.
At the moment I'm using the set multicycle path commands: set_multicycle_path -from [x] to [y] -setup -end 50 set_multicycle_path -from [x] to [y] -hold -end 49 Everything compiled and Time Quest is now telling me I meet the timing requirements. However, it also said it is adding in large delay routing in order to meet hold timing. All I'm doing is putting an enable to the register, which comes from a count delay off the main clock. This is just extending the latch edge and that's it. Is it normal for Quartus to add large routing delays to meet hold requirements when using multicycle paths?
