Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi rawbus,
I see there two possible solution to your problem. Either set_multicycle_path and set it e.g. to 10 clock cycles. So it is still smaller then 1 us but should be enough for the fitter and timing analyzer. Or us another division algorithm that has a smaller delay. What about doing it with the pen and paper method so you compute 1 bit per clock but this just needs a comparator, bit shift and subtractor. This also will reduce the logic count. Best Regards, Mathias