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I want the flip flop to be triggered on both posedge and negedge of my data input signal.
I imagined the clk port of the FF is connected to an output of an OR gate, and triggered on posedge. This OR gate has (clk, data, invdata) as its inputs. whats wrong with such setup?
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I modified the code you got from jacobjones, because "edge" is a reserved keyword in Verilog. The code could not compiled by Quartus.
I inserted two edge detectors, which looks for the rising and the falling edge of your input signal. I check at least the basic function.
module ocd(
input clk, // clock
input reset_n, // active low reset
input data_in,
output reg data_out
);
reg last_data;
reg [2:0] counter;
wire edge_pos /* synthesis keep */;
wire edge_neg /* synthesis keep */;
// wire edge;
// assign edge = last_data ^ data_in;
assign edge_pos = !last_data & data_in; // detects posedge in data_in
assign edge_neg = last_data & !data_in; // detects negedge in data_in
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
data_out <= 1'b0;
last_data <= 1'b0;
counter <= 3'd0;
end else begin
last_data <= data_in;
counter <= counter + 3'd1;
if(edge_pos ^ edge_neg ) counter <= 3'd3;
// if(edge) counter <= 3'd3;
else if(counter == 5) begin
counter <= 3'd1;
data_out <= data_in;
end
end
end
endmodule
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