This short verilog code is not working

It's not possible to trigger a single FF on both edges, neither a discrete device, e. g. a 74HC74 nor a FPGA FF. It doesn't work directly or by any trick (as defining an inverted signal).

To design logic, that is sensitive for both edges, you can use two FFs and combine the results, but you have to be careful not to generate glitches in the output.

Another option is synchronous edge detection by a sufficient fast clock.