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The original code is edge sensitive only for posedge(invdata) and level sensitive for clk and data. The code isn't generally unsynthesizable but most likely neither intended this way nor creating any meaningful logic behaviour. Additionally latching on data == 1 and sampling on posedge(invdata) respectively negedge(data) creates a timing violation for the edge triggered flip-flop.
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I want the flip flop to be triggered on both posedge and negedge of my data input signal.
I imagined the clk port of the FF is connected to an output of an OR gate, and triggered on posedge. This OR gate has (clk, data, invdata) as its inputs. whats wrong with such setup?
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