This short verilog code is not working

A few things to mention:

1 - It looks like you're getting confused in your signal names. You're using a signal called data but you're also using a signal called input. Are they supposed to be the same thing?

2 - You should never use the names "input" or "output" to name signals. Those are keywords in Verilog and should only be used when declaring inputs and outputs to a module, task, or function.

3 - You're event triggerred always block. You need to keep in mind that what you are writing is going to be turned into hardware. Flip-flops in hardware have a single clock input. You cannot use a rising and falling edge of a signal as a clock input to a flip-flop. Your code is actually not synthesizable. You have a clock input, data input, and a asynchronous set and/or reset signal at your disposal.

4 - It's good practice to provide a reset signal to initialize your registers to a pre-determined state.

Does this meet your needs? I haven't compiled it so there might be a syntax error or two:

module ocd(
    input       clk,            // clock
    input       reset_n,        // active low reset
    input       data_in,
    output      data_out
);
reg         last_data;
reg    counter;
wire        edge;
assign      edge = last_data ^ data_in;
always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
                        data_out    <= 1'b0;
                        last_data   <= 1'b0;
                        counter     <= 3'd0;
    end else begin
                        last_data   <= data_in;
                        counter     <= counter + 3'd1;
        if(edge)        counter     <= 3'd3;
        else if(counter == 5) begin
                        counter     <= 3'd1;
                        data_out    <= data_in;
        end
    end
end
endmodule