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Altera_Forum's avatar
Altera_Forum
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10 years ago

This is a typical program for traffic light controller without a test bench

I got two errors while synthesizing the program and the VHDL code is .......... Library IEEE; use IEEE.std_logic_1164.all; package lights is subtype light is bit_vector(0 to 1); c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Error is quite clear. You can't have a sensitivity list and a wait statement in a process. I suggest you read a vhdl tutorial to get valid process templates for various constructs