This is a typical program for traffic light controller without a test bench

I got two errors while synthesizing the program and the VHDL code is ..........

Library IEEE;

use IEEE.std_logic_1164.all;

package lights is

subtype light is bit_vector(0 to 1);

constant red: light := B"00";

constant green : light := B"01";

constant yellow : light := B"10";

end lights;

use WORK.lights.all;

entity traff is

port(clock : in Bit;

reset: in Bit;

cars : in Bit;

short,long : in Bit;

highway_light : out light := green;

farm_light : out light := red;

start_timer : out Bit

);

end;

-- define light controllers behavior

=>

architecture register_transfer of traff is

type ctrl_state_type is(hg,hy,fg,fy);

signal ctrl_state,ctrl_next : ctrl_state_type := hg;

begin

ctrl_proc_combin : process(ctrl_state,short,long,cars)

begin

if reset = '1' then

ctrl_next <=hg;

else

case ctrl_state is

when hg =>

highway_light <= green; farm_light <= red;

if (cars and long )= '1' then

ctrl_next <= hy; start_timer <='1';

else

ctrl_next <=hg; start_timer <= '0';

end if;

when hy =>

highway_light <= yellow;farm_light <= red;

if short = '1' then

ctrl_next <= hg; start_timer <= '1';

else

ctrl_next <= hy; start_timer <= '0';

end if;

when fg =>

highway_light <= red; farm_light <= green;

if ( not cars or long ) = '1' then

ctrl_next <= fy ; start_timer <= '1';

else

ctrl_next <= fg ; start_timer <= '0';

end if;

when fy =>

highway_light <= red; farm_light <= yellow;

if short = '1' then

ctrl_next <= hg;start_timer <= '1';

else

ctrl_next <= fy; start_timer <= '0';

end if;

end case;

end if;

end process ctrl_proc_combin;

=> sync:process(CLOCK)

begin

wait until CLOCK'event and CLOCK = '1';

ctrl_state <= ctrl_next;

end process sync;

end register_transfer;

And my error is

Line 67: Process cannot have both a wait statement and a sensitivity list.

Line 24: Unit <register_transfer> ignored due to previous errors.