This circuit to Verilog model.. Is it possible?

You should specifiy the signal processing exactly. The schematic doesn't seem to implement a "bias". I guess you meaned to sketch a high-pass rather than the shown low-pass.

But either if it's a high- or low-pass, it implements a time constant that would be approximated by a z-domain difference equation, the same for the output low-pass. If you don't actually mean it, correct the schematic.