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sunin's avatar
sunin
Icon for New Contributor rankNew Contributor
3 years ago

The routing delay is 0 ns in quartus chipplanner

I designed a program about TDC. However,i found the routing delay is 0 ns when i check its timming by Timequest.Shown below, the Tco is 0.073ns,but the routing delay is 0 ns. chip planner ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Sorry for the delay in response. It seems that the timing path comes from the LPM_ADD_SUB IP itself.

I believe the IP function correctly and the 0ns routing delay could be an expected behavior.

Do you see any problem when you try to run simulation with the current design?