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sunin's avatar
sunin
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3 years ago

The routing delay is 0 ns in quartus chipplanner

I designed a program about TDC. However,i found the routing delay is 0 ns when i check its timming by Timequest.Shown below, the Tco is 0.073ns,but the routing delay is 0 ns. chip planner ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

I do not have the answer with the current info provided.

I will need to get your design to further investigate this. Could you share the design .qar file?

Which Quartus Pro version and devices are you using?


sunin's avatar
sunin
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3 years ago

Are you still there？ In my opinion, thare are different delays between adjacent LEs especially between adjacent LABs. However, the routing delay created in 16-bit adder is not like this. The 16-bit adder project shown below has played STA, and the delays are similar. I will so appreciate it if you can reply to me ==||