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sunin's avatar
sunin
Icon for New Contributor rankNew Contributor
3 years ago

The routing delay is 0 ns in quartus chipplanner

I designed a program about TDC. However,i found the routing delay is 0 ns when i check its timming by Timequest.Shown below, the Tco is 0.073ns,but the routing delay is 0 ns. chip planner ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

I do not have the answer with the current info provided.

I will need to get your design to further investigate this. Could you share the design .qar file?

Which Quartus Pro version and devices are you using?


sunin's avatar
sunin
Icon for New Contributor rankNew Contributor
3 years ago

Thanks for your response! The file below is a simble project about 16_bit adder. It use the delay chain resourse shown in the chip-planner. In this case, there is no extra delay between the adjacent LABs. In my humble opinion, the routing delay between LABs should be bigger than those between LEs. Your reply is very helpful to me!

Best wishes for you!