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sunin's avatar
sunin
Icon for New Contributor rankNew Contributor
3 years ago

The routing delay is 0 ns in quartus chipplanner

I designed a program about TDC. However,i found the routing delay is 0 ns when i check its timming by Timequest.Shown below, the Tco is 0.073ns,but the routing delay is 0 ns. chip planner ...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Wow, that is a huge negative slack! I will look into why the clock skew is so high and start work from there first. 2.347 is too high.

Before that, check if the timing path is relevant as Timing Analyzer will analyze all paths. If not, set false path to tell the tool to exclude that path.

You may checkout the Best Design Practices for Timing Closure:

https://www.youtube.com/watch?v=UGGkKZylJBo&t=122s


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.


sunin's avatar
sunin
Icon for New Contributor rankNew Contributor
3 years ago

In fact, i have confirmed that the 0 ns routing delay has no connection with the huge slack earlier this evening. And now, i am more concerned about why the 0 ns routing delay persist... I have been stumped until now and didn't know what else to do...