Forum Discussion
FrankOuO
New Contributor
New ContributorThe result of Clock divider's Waveform simulation doesn't work properly with top module
Hello, everyone
I just wrote a very simple clock divider by 2,
and I want to add this module: clock_out.v to my top module named light.v
(from the tutorial: Using_the_SDRAM)
But if I running ...
RichardT_altera
Super Contributor
Super ContributorHi @FrankOuO
Sorry for the delay in response. Do you need further help regarding to this case? Do you able to solve the issue by yourself?
I would recommend to write a testbench and simulate it using the Modelsim Intel FPGA Starter Edition instead of waveform simulation.
You may checkout the webpage below for an example.
https://www.fpga4student.com/2017/08/verilog-code-for-clock-divider-on-fpga.html
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
