the problem of timing constraint

Ahh, I missed the oExt delay. This isn't an internal transfer, where clock skew is bad, but an external transfer to an output port. That being said, you're latch clock delay is usually 0(unless a source synchronous output), but in your case it's negative. The problem is that you're using the PLL clock as the external clock. The PLL clock name should never be used in a set_input/output_delay constraint. The -clock option of this constraint is saying what clock drives the external register off chip. The analysis you're getting will look at the clock tree up to the PLL output and then have it magically jump off chip. I talk about this in the Getting Started section of the user guide:

http://www.alterawiki.com/wiki/timequest_user_guide

Anyway, create a virtual clock:

create_clock -name clk_ext -period 6.666

Then have your I/O constraints based on this, e.g.:

set_output_delay -max 2.5 -clock clk_ext [all_outputs]

The Clock Network Delay on your latch clock will go to 0, which will help setup timing and it should meet timing. (Note that your setup time is 6.666ns and your external delay is 2.5ns, so you're basically asking the FPGA to get its data out in 6.666-2.5 ns, or 4.166ns.

Also, be sure to do your timing analysis in TimeQuest, not just that info message you're posting. There is a more detailed breakdown there.