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in simulation a code for QAM mapping used in OFDM .. the code is working great but i have a problem
the output is shifted by one clock
the output that should appear in clk 1 with input11 appears in clk 2 with input 2 and so on
the code is
this is not clearly my code :)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity qam is
port (
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(1 downto 0);
Iout : out std_logic_vector(11 downto 0);
Qout : out std_logic_vector(11 downto 0));
end qam;
architecture qam of qam is
begin
process (clk, rst)
constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
begin
if rst = '1' then
Iout <= (others => '0');
Qout <= (others => '0');
elsif clk'event and clk = '1' then
case input is
when "00" =>
Iout <= mais1;
Qout <= mais1;
when "01" =>
Iout <= menos1;
Qout <= mais1;
when "10" =>
Iout <= mais1;
Qout <= menos1;
when others =>
Iout <= menos1;
Qout <= menos1;
end case;
end if;
end process;
end qam;
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if one clock latency matters to you (and I doubt it) then remove that clock and make your assignments combinatorial
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