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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

The loanIO confusions

Hi, What I want to do is loan the GPIO 57~60 on the cyclone V soc board to the FPGA, these four pins act as SPIM0-CLK, SPIM0-MOSI, SPIM0-MISO and SPIM0-SS0. And these pins are connected to J32 pin...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi CAlex,


There was some on-going conversations from the previous comments. I didnt manage to understand the problems which are still not being resolved on your end.

Would like to know the focus on the problems that are still present?


Thanks.

Regards,

Aik Eu


CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Hi

"

Now Im totally confused by the directions:

I have three parts:

hardware IO : HTX , HRX.

software IO :STX,SRX.

generally HTX -> SRX , HRX <- STX.

Now I borrowed the HPS IO to the FPGA, they are MISO(59) and MOSI(58).

If I didnt misunderstand the meaning of h2f_loan_io_in/out/oe

Version 1

MISO(59) should be HPS output(oe = 1) linked to HRX,which means links to STX

MOSI(58) should be HPS input(oe = 0) linked to HTX,which means links to SRX

However

loan_io_in means FPGA output to HPS input

Version 2

MISO(59) should be HPS output (oe = 1) linked to SRX,which means links to HTX

MOSI(58) should be HPS input (oe = 0) linked to STX,which means links to HRX

Who can tell me which one is right? <---------------- not solved

And do I need to write the HPS code / pre-loader, if needed ,how? (solved)

Reguards.

"

I just want to know when I wrote a UART RS232 IP with SRX and STX, linked to the hardware HTx and HRx, the LoanIO MISO and MOSI should be output or input (set oe == 1 or 0 , wire loanIO_out/in assigned to SRX and STX).

Reguards