Forum Discussion
ContributorThe loanIO confusions
ContributorHi,
I've already set the GPIO 58 and 59 as loan IO, and export the IOs.
Mux Table setting
Pin planner setting
By using the Loan IO 58 and 59, I set the 58 as in and linked to my other RS232 module RXD and 59 as out linked to TXD.
top level setting 1
top level setting 2
As mentioned by Accessing HPS Devices from the FPGA (intel.com) chap 2.2,
In HPS baremetal code I set the GENERALIO_10/11 and GPLINMUX58/59 to 0x0
HPS baremetal settings
According to Cyclone V HPS Register Address Map and Definitions - GENERALIO10 (intel.com)
(For example general IO 10 and MUX58)
general IO 10
MUX 58
The pin is linked to Genral IO 10 as a loan IO 58.
After doing that I checked the value of these registers
their low 2 bits are =2'b00
And in FPGA board I sent the signal to the pin loan_io_out_59 but I didnt receive any signal from that pin.
Did I do something wrong with that?
What's the right steps to deal with loanIO under baremetal environment?
Reguards.
ContributorAlso, I've been checking the HPS reference book:
"Each LoanIO port has an input, output, and output enable, which directly controls the HPS IO functions.
The LoanIO only operates when the HPS registers have been set up in the pre-loader to allow their
operation. The LoanIO are asynchronous, thus no clocking is required."
So what is the necessary setting of the pre-loader? and HOW?
