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This is just a VHDL library to declare the std_ulogic, std_ulogic_vector (and std_logic etc) types. Because of the VHDL typing rules you cannot do alot without them for synthesisable logic.
The libraries tab in quartus are for user libraries. it also dictates the search path for any .inc files (if for some reason you're using AHDL).
So there is no way to use std_logic_1164 in verilog because it doesnt exist. it is a VHDL only thing because of the way the language works.
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Thanks very much. Yes, Verilog does not need VHDL library. But user libraries can be used for both in VHDL and Verilog, right?
Another question I have is: what kind of files is inside user libraries? Customized IP?
Thanks.
Honored Contributor
