the "latch" problem

substitute your instruction:

default:begin end

with

default:

begin

RsutCPID0<=1'bx;

Add all the signals that are defined in the procedural block

end

In the sensitivity list : always @(CurloopCal)

add the signals that are on the right side of the assignments such as: Cerr0

always @(CurloopCal,Cerr0)

This won't solve all the problems. As example you write: sumce <= sumce+Cerr0;

That can waork only if a register holds the sumce value and the procedural block is sychronized with the clock.

I suggest to read a book on Verilog for synthesis.