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Altera_Forum
Honored Contributor
10 years agoThe difference between simulation and reality and warning (332060)
Hello, i am writing to you because i have some differences between simulation and reality. Before I start to write about warning mentioned above, I would like to tell about symptoms.
I assign value for register, for example 32:output out;
reg init= 6’d32;
assign out=init; (This code is very simplicated) In simulation value of output is 32. In reality it is 0. I have no idea why. So I wonder if it has something in common with warning: --- Quote Start --- Warning (332060): Node: Debouncer:b2v_Debouncer|Knob_Debouncer:KD25|Action[1] was determined to be a clock but was found without an associated clock assignment. --- Quote End --- I use mechanical encoders to increase or decrease a value of register. So I use posedge of signal from debouncer (As a clock in always block) to change value of this register. Because of that is not periodic signal, I can't assign all atributess in TimeQuest Timing Analyzer. I can’t define it as a clock. Is this something that could make problems with registers mentoned above? Thank you for all your replies.2 Replies
- Altera_Forum
Honored Contributor
Hello Lutzek,
You might consider:
Since encoder signals do not run on 50MHZ, but much slower, this can help. For performance reasons, the rest of your logic runs at clock speed, so there is not much added value introducing the encoder signal as a clock. Debouncing could be not necessary, you are not pressing a button, most encoders have electronics internally that prevent bouncing. Best Regards, Johi.output out; reg init; reg counter; assign init=6'd32; assign out=init; reg statePrev; always @(posedge CLOCK_50) begin if (encoderInput!=statePrev) begin statePrev<=encoderInput; counter<=counter+1; end; end; - Altera_Forum
Honored Contributor
Initial value assignments in (reg [5:0] init= 6’d32; ) will not synthesize. If you need to initialize a register, use reset pin and assign its initial value when that reset activates.
For your example, try the following code: output [5:0] out; reg [5:0] init; assign init = 6’d32; assign out=init; The output will be 6'd32 constantly. For clock constraining, you should consider the worst case frequency of your switch and define a clock with the highest frequency which may occur. Keep in mind however that this is NOT a good practice. Instead use synchronous sampling of the switch using a sufficiently high speed clock source.