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Altera_Forum
Honored Contributor
Honored Contributorthe connection of multiple modules
module LED(clk_div320k,rst,out,common1,common2,common3,common4,BCD_hunds,BCD_tens,BCD_units); input clk_div320k,rst,BCD_hunds,BCD_tens,BCD_units; output reg [6:0]out; output reg common1,common...
Altera_ForumHonored Contributor
Honored ContributorRefer to a very good article covering this - "verilog: how to instantiate a module (http://stackoverflow.com/questions/20066850/verilog-how-to-instantiate-a-module)".
You can also look at "verilog hdl syntax and semantics (http://www.asic-world.com/verilog/syntax2.html)". Cheers, Alex
