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Altera_Forum
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17 years ago

the clock network delay is different between Timequest report and chip planner

i am learning timequest and sdc, but now i have some confusion with the difference of the clock network delay between Timequest report and chip planner. http://www.alteraforum.com/forum/attachment...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Note that even in the slow model, if you do a setup analysis or hold analysis on the exact same path, you will end up with different numbers(for 65nm and newer families). This is correct, but the Chip Planner won't convey that.