Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHello,
Really appreciate the response. Yeah I see online examples from Altera regarding the BFM s and the way those can be used to test the IP cores. Hope those will be useful to me. The counter design is a simple one taken from the webpage http://www.alterawiki.com/wiki/simulating_designs_with_lower-level_qsys_systems It is just a plain counter with out any Avalon interfaces (so that a testbench is sufficient). Infact the counter is not an IP, just a verilog module. Thank You, Akhil