Honored ContributorDear all,
I have problem here; i want to make a testbench using ModelSim but i cant. I write the testbench code in Quartus ii, then i follow the steps of one of the Altera Guru from this forum for export the file to ModelSim. But, it does not work. My question is how can i make the testbench in ModelSim after i write the testbench code in Quartus ii? Anyone can help me please.Thanks
Honored ContributorHow have you written the testbench? if you write it in VHDL or Verilog you can run it direct from modelsim.
Honored ContributorDear Tricky,
Yes, i already write the testbench in VHDL..How to run the testbench with ModelSim? Can you give the steps? Thanks for replyHonored Contributorin modelsim console window:
cd /directory where the VHDL is/ vlib work vcom my_vhdl_file.vhd (do this for every VHDL file) vsim my_testbench run XnsHonored ContributorDear Tricky,
Sorry i am very new with ModelSim..i don't understand about your steps. Can you give a detail step? Thanks for replyHonored Contributor1. Load modelsim
2. highlight the transcript window, you can type in here 3. type all the commands I just gave youHonored ContributorDear Tricky,
Did you mean i need to write the code that you give above in ModelSim? Then, what about my testbench VHDL code in Quartus ii? How they connected? i not clear about that. Thanks for replyHonored Contributorthe VHDL code is just a text file. You just need to navigate to the directroy where you created it.
Honored ContributorDear Tricky,
I still don't understand your steps.I really lost. Btw, thanks for reply
