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Hello
automatic (functional and timing )simulation can be finshed inside quartus ii by setting the design to run in quartus and use EDA tool for simulation, and this should be used the test bench code for the project and start elabobation procces before running the eda simulation tool
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To repeat...Quartus is
not a simulation tool, it is a synthesis tool. The setting that I think you are referring to in Quartus for EDA tool for simulation does
not run a simulation, what it does is tell Quartus which tool you are using for simulation.
Quartus can then be setup to automatically run the simulation if you want, but this is not required. You can simply open the simulator, compile the source files and run the simulation without involving Quartus at all.
The problem you seem to be having with not being able to analyze and elaborate the design in Quartus is caused by one of two things:
- You have syntax problems in your design
- You are including the testbench file into your Quartus project.
Assuming that the problem is the testbench has been included into your Quartus project you have two solutions:
- Remove the testbench file into your Quartus project.
- Add pragmas at the start and end of the architecture as indicated below
ARCHITECTURE Block4CLA_arch OF Block4CLA_vhd_tst IS
...
begin
--synthesis translate_off
... All of the current architecture stuff that you have would go here.
The translate_off/on pragmas tell Quartus to ignore whatever is in between.
--synthesis translate_on
...
END Block4CLA_arch;
Kevin Jennings
Honored Contributor
