Test Bench Settings

Dear all,

a small update.

Reading the manual it says that "Use test bench to perform VHDL simulation" must be checked for Gate Level simulation.

However, even without this checked I can execute Tools -> Run EDA Simulation Tool -> EDA Gate level simulation

and see delays in my simulated circuit.

Am I doing something wrong?

Is it a Gate Level simulation what I'm running or something is missing in it since I do not check the "Use test bench to perform VHDL simulation" checkbox?

Thx.