Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

test bench for d flip flop

I have write a code in vhdl for d flip flop as below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity d_ff_en is Port...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You don't stimulate 'en', so the d_ff_en will not change its status.

A tip: do not give a default value to the signals in a testbench, that way ModelSim will flag the 'X'-value (or perhaps 'U') by drawing a red trace. So you know which signals are not driven.