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Altera_Forum
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13 years ago

test bench for d flip flop

I have write a code in vhdl for d flip flop as below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity d_ff_en is Port...
Altera_Forum's avatar
Altera_Forum
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13 years ago

if there is a syntax error it should tell what line the error is on.