Petrov1
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New ContributorTest a Verilog module via System Verilog
Trying to test a Verilog module via System Verilog. I'm analysing the RTL Simulation and I get the error: Error (10170): Verilog HDL syntax error at Test1.sv(29) near text: "program"; expecting a des...
I checked and it seems that the 3.4 Programs construct - whereby "The program building block is enclosed between the keywords program...endprogram", is currently Not supported in the Quartus synthesis tools.
To know more about the constructs supported. You may checkout the webpages below:
Verilog HDL Synthesis Support
SystemVerilog Synthesis Support
