Tco Constraints

Hi Batfink,

Thanks for the info. Yes I´m using a Flex10K and I tried your suggestion. The results were positive. I tried placing certain nodes where I saw excess delay in the same LAB and I did see some savings..enough to make timing on certain paths.

I tried doing this at 50MHz where the design is right on the dge of making timing, but the main goal is to have this design working at 64MHz. At the moment there are too many paths which do not make timing and as you said the knock on effect is noticable.

For this design to run at 64MHz, certain parts of the code will have to be re-done. Once this is achieved, if the design is much closer, I think using cliques could be very useful.

Just one question. You mentioned that cliques are only available on ACEX 1K, FLEX 10K, FLEX 6000, or Mercury devices, so I was just wondering how can this trick be implemented on the newer devices?

Also I was wondering why Quartus would not implement something like this automatically, to guide the fitter when it sees certain paths not making timing?

I´m sure that quartus is doing something along those lines, but that there is a good explanation as to why some paths still fail.

Would this be an advantage of using a 3rd party synthesis tool? that perhaps they would synthesis the design differently and obtain better results?

Anyway although this particular project has been a real head-wrecker, I´ve certainly learned a lot of new stuff. I never would have known about cliques for sure and probably wouldn´t have have learned as much about timing issues, so once again thanks for all the help.