Tco Constraints

Digging through the Quartus help it would appear that IC is the interconnection delay and CELL is the cell (i.e. logic propagation) delay. Apparently the routing forms the majority of the delay in modern chips so this would seem to tie up.

Understanding the routing delay and how Quartus has laid the chip out can help you squeeze a bit more out of the chip - e.g. where you can see a critical delay between two cells which are placed wide apart, you can use cliques to put them in the same row or LAB. You won't get that much gain by going in and looking at the routing in this way (a few ns in certain bits) but if you're right on the edge of meeting your timing constraints it can be a help.

Looking at the fan-out can help you make changes to your design - e.g. adding pipelining were you have multiple levels of combinatorial logic - if you have say an adder and a mux followed by another adder between two registers and this appears to be the critical path, then stick a layer of registers between one of the adders and the mux - uses more resources but less combinatorial logic between any two registers and so the overall clock speed will increase.

Also there are some settings in Quartus to automatically add cells (combinatorial logic) and registers to improve timing - from memory I think these ar ein the fitter settings. basically by duplicating registers or cells, you can reduce the fanout and ease the routing delay.

Just a note of caution when you're looking at fast edges - use a fast scope with fast probes and don't have a long earth clip - take the earth clip off and wrap a short length of stiff bare-metal wire around the earth case of the probe - this will give you a very short earth which you can touch onto your circuit at a point (earth of course) very close to the point you are actually probing. This will give you a very low inductance earth connection and will give you a much better picture of what you're looking at. Check out oscillator outputs like this - with a standard earth clip you can get a nasty looking sine wave, with a low inductance earth you can get a nice square wave - the difference is quite surprising.

This sort of work is wquite frustrating hen you're doing it but I do think that experience of bad designs and poor documentation from other people can make you a better engineer in the long run.

Good luck