Tco Constraints

Batfink, good idea. I am hoping to get around to looking at the outputs on a scope and comparing them with the 2 different programs. If no significant difference exists, i am hoping to disable the slow slew rate constraints.

Rysc, thanks for the advice, I hadn´t been exapnding the paths like that before. But doing so provides a wealth of information and its much simpler to find where exactly in the desgin the problems exist.

I can understand and follow what Quartus is telling me, but there are some terms that I do not fully understand.

For example I am looking at the worst case setup warning and under the "- longest register to register delay" section, Quartus details 5 different sections that make up the path between the 2 registers, the 2 Reg nodes and 3 combinational nodes. For each one it gives the delay in the signal getting there but it calcualtes the delay using the following formula:

Info: 2: + IC(4.500 ns) + CELL(1.400 ns) = 5.900 ns; Loc. = LC1_D30; Fanout = 54; COMB Node = 'vic068:vic068_inst_1|local_if:local_if_inst_1|lm_mux:lm_mux_inst_1|i_m_blt~53'

I don´t understand what the IC delay refers to and what the Cell delay refers to. Although they both add up to 5.9 ns which is the important part. But I´m just curious as to what the classic timing anlyzer is actually doing.

Again many thanks.