Tco Constraints

Hi,

I have seen a slow slew time contraint on each of the output pins in the design. I suppose its obvious what it does, and in the assignment editor it says that this value will affect any Tco constraint which apply to the pins. What I am wondering is, would applying a slow slew rate constraint to each pin be nessesery under normal circumstances? I have seen that by disabling this constraint, I can see huge improvements in the timings.

What is the danger in disabling them? Just that more noise may be generated and signals may be received incorrectly?

The design is used as a VME bus controller, so the interface with the local processor and the actual VME bus is asynchronous. Given that fact that the interface is asynchronous and precautions would be taken to ensure that all signals are read correctly to avoid metastability etc, would bit be ok to remove these constraints. Maybe this is difficult for anyone to answear given that they are not familiar with the board etc, but any adivice would be appreciated.

Just another query I have regarding the Tco constraints. Rysc said yesterday that really a Tco constraint should be from input pin to output pin, as if it is from a register to output pin, the delay could from an input pin to the register could change. But if the inputs enters the FPGA and is clocked through various components before finally being clocked out, what is the best way to constrain this. Is it by constraing every path between the clock cycles from the input pin to the output. in which case it would be aceptable to place Tco contraints from register inputs to FPGA outputs

One final thing on a slightly different topic:

When I look at the clock setup time warnings, Quartus reports the required longest P2P time and the actual longest P2P time. What is the difference in these? and why is the fmax calculated using a differnt value.

For example one warning appears as follows:

Required seup relationship: 20 ns (50 MHz)

Required longest P2P Time: 18.8 ns

Actual Longest P2P Time: 19.8 ns

Actual Fmax: 47.62 MHz ( period = 21.000 ns )

Why does fmax have a period of 21ns and what is the difference in the required and actual P2P times?

Again many thanks for your help.