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Also Quartus says that the time value specified in a Tco constraint "always represents an external pin to pin delay". What exactly does altera mean by this: a register input to output pin or an input pin to output pin?
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As I understood this, you have a clock somewhere in your FPGA which ultimately comes from an input pin.
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The constraint in question is a single point Tco costraint it seems. This constraint has an internal reset signal in the 'To' field, so Quartus, if I understand correctly, will attempt to meet the Tco time specified from this signal to each output pin that it can effect. Am I correct on this?
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I'm not quite sure what your particular "From * To reset" constraint would be doing to be honest - I would have thought that it would get ignored because reset is not an output pin. I would be surprised and worried if Quartus was transforming that constraint into "From reset To everything_else_that_depends_on_reset". I'm not saying that's not what's going on, but if it is what's going on then it's very weird and illogical.
from Rysc:
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Also, I think a Tco can be an asynchronous reset, i.e. if a reset comes in, goes through the register and to the output pin, much like a clock would.
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I had understood that Tco was strictly for a clock and to achieve this for a reset, one would have to use tpd - again I wouldn't swear blind to this and Rysc may well be right.
Basically I can see no reason why you would actually want to specify the tco for an internal signal - why would you want a particular register's output to change within x ns of the clock edge - you don't care how fast it changes as long as it's fast enough to meet the setup times of downstream logic and registers to meet the clock requirements. If it meets the clock requirements then why would you want to make it faster - you're just giving Quartus a harder job to do.
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...so i suppose I will just relax this constraint and see how this work out in the simulation later.
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- I would say strip it out and check your simulation afterwards.
Frankly I think you're in a bloody difficult position - you've obviously had an undocumented design dumped on you which was done by somebody who may not have fully understood what all the constraints meant and so ended up over-constraining the design. You could chuck out all of the constraints and then look at the design yourself and work out from scratch what they should be - potentially risky and I'm not even sure that I'd want to attempt it myself but it depends on how confident you are of your abilities and how confident you are that the majority of the existing constraints aren't a load of guff.
Good luck - you really have my sympathy on this one.
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