Tco Constraints

Tco should be from pin to pin. If it started at some point inside the chip, then in general it would not be very useful. On one compile the delay to that arbitrary point could be 1ns, on the next compile it could be 10ns, and the time your data comes out would be all over the place, yet Quartus would report the same Tco since it ignored the variance up to that point.

That being said, I'm not sure exactly what's being analyzed in your case. Right-click on it in the Tco report and do a List Path. You should see a message added to the window below, which can be opened to get more detail. This should tell you everything that it's analyzing and in much more detail. I can't tell you what the original designers intent was, which is the difficult problem you need to tackle.

Also, I think a Tco can be an asynchronous reset, i.e. if a reset comes in, goes through the register and to the output pin, much like a clock would.