Tco Constraints

Thank you for both replies.

Forgive me but I´m still a little confused about the Tco constraint as I always thought that it was the time from a clock edge until the signal appears at an output pin, as this was the description given in the assignment editor in Quartus. It wouldn´t be the first time that i have misinterpretted it though. Also Quartus says that the time value specified in a Tco constraint "always represents an external pin to pin delay". What exactly does altera mean by this: a register input to output pin or an input pin to output pin?

Is it possible to place a Tco between 2 signals and then the Tco could mean the time from the clk edge until the output appears at the register output?

The constraint in question is a single point Tco costraint it seems. This constraint has an internal reset signal in the 'To' field, so Quartus, if I understand correctly, will attempt to meet the Tco time specified from this signal to each output pin that it can effect. Am I correct on this?

So now the warning that I see in the timing report makes sense (I initially thought it seemed unrelated, but the original constraint did not appear in the ignored constraints list), Quartus seems to be saying that from this signal to one of the outputs that the reset can affect does not meet the timing constraint.

I have had a look at the code and can see nothing abovious that I can do to improve the timing, so i suppose I will just relax this constraint and see how this work out in the simulation later.

Many thanks.