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What I understand a Tco constraint does is that it specifies the maximum acceptable time for a signal at the input to a register on a clock edge to appear at the output pin. Is this what it actually specifies?
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Tco is the time from a clock edge to the output of the register actually changing. In your case the delay between a clock edge and your reset signal being activated. I would expect your clock signal to be in the "from" field.
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I don´t understand why an error is not produced by quartus and why this causes the warning mentioned above
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Quartus sometimes just ignores invalid constraints and assignments. Is there a section in the report or console where it says something like "found x invalid timing requirements" - if you find this and expand it you may find this assignment in there.
According to the Quartus help on tco "This time always represents an external pin-to-pin delay" so I think you're probably safe to remove the assignment in question - Quartus should handle the internal timing requirements based on the clock requirement.
Is there a tpd requirement associated with your warning message - i.e. your man might have wanted the reset to propagate to the outputs in 14 ns.
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Are there any guidelines for placing Tco constaints that i should be aware of, if I want to verify or change existing constraints.
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I thin kit's just a case of looking at your design and working out the relationship between the signals on the board.
Honored Contributor
