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Altera_Forum
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15 years ago

Tcl with Simulation (Vector Wave Form Files)

I have created a VHDL project in Quartus and am now trying to create a functional test bench for it using Tcl. I have used the "Generate Tcl File for Project" to create a base Tcl file. Now, I am tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I am fairly new to VHDL.

And have been looking up literature into reading files and writing files. What is the best way to perform this task. In the scope of reading from files and setting strings as Inputs for a line, and then running through clock cycles. And then outputting results onto a text file.

Thanks.