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Altera_Forum's avatar
Altera_Forum
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15 years ago

Tcl with Simulation (Vector Wave Form Files)

I have created a VHDL project in Quartus and am now trying to create a functional test bench for it using Tcl. I have used the "Generate Tcl File for Project" to create a base Tcl file. Now, I am tr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

But why use TCL to create testbench. Seems to me the wrong hard path if at all possible.

Just write a testbench in HDL. You can generate vectors, read files, write to files, perform some complex maths at ease and inject your rtl design with the nice and bad vectors. check against the ref outputs...etc.