Forum Discussion
Hi KhaiY,
it solves not the initial error mentioned in the thread, which YTagu5 has opened. It solves the minimal working design which I thought is similar to our problem. It wasn't the same root cause than in our design. The minimal working design is just the example design which can be created in the platform designer for lvds cores. For this example, the solution with derive_pll_clocks -create_base_clocks works.
However, the solution in Gabriele's post also solved our issue. I put the solution there to the sdc_util.tcl files in both cores, lvds_rx and lvds_tx.
Sorry, I didn't check his thread further, since it sounded for me like a different error due to your suggestion to create a new thread.
I will also check if the solution in Gabriele's thread will remove the warnings caused by the file lvds_rx_altera_lvds_core20_191_5u346cy.sdc. I will write my findings in his thread.
Thank you.
Michael